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TUSK INNOVATIONSGlobal Private Limited
FLAGSHIP PRODUCT•OPEN SOURCE RUNTIME

Electronics Agent Kit (EAK)

Intent In. Engineering Model Out. Verified Engineering Artifacts Out.

EAK is an open-source, AI-native electronics engineering system and runtime. It maintains a canonical, provenance-rich engineering model, executes deterministic physics and DRC rules, validates AI proposals, and commits only verified hardware state.

Core Definition

What is Electronics Agent Kit?

EAK is not a chatbot wrapper. It is a full engineering runtime built from first principles in Rust.

The Canonical Engineering Model

Unlike conventional desktop EDA software where state is scattered across loose text files and schematic sheets, EAK maintains a centralized, event-sourced canonical engineering model.

This canonical model contains: intent, requirements, constraints, decisions, assumptions, evidence, components, pins, nets, topology, schematic representations, PCB layout geometry, physical verification results, and complete revision provenance.

The Seam Between AI and Physics

In EAK, AI models never directly mutate authoritative hardware state. Instead, models propose capabilities through a strictly validated seam.

The EAK kernel applies deterministic engineering rules — pure functions checking Ohm’s law, voltage drop limits, differential pair geometry, and pin electrical types. Only proposals that satisfy all invariants are committed to the event log.

Architectural Integrity

Non-Negotiable Principles

Enforced at compile-time and through the kernel commit pipeline.

P1

EAK Runtime is the Source of Truth

No external CAD tool, editor, or filesystem holds authoritative engineering state.

P2

External Formats are Never Truth

.kicad_pcb, .kicad_sch, .json, and .yaml are import/export formats only.

P3

AI Never Writes Directly to State

All AI mutations must pass through the kernel’s validated capability seam.

P4

Deterministic Rules Stay Deterministic

Physics, geometry, and connectivity rules are pure, reproducible functions.

P5

Provenance is Mandatory

Every fact knows its exact origin: human input, datasheet excerpt, or AI inference.

P6

Engineering State is Replayable

Event log + deterministic fold reconstructs the exact project state on any machine.

P7

Physical Quantities Remain Typed

Units, tolerances, and thermal deratings are first-class types (eak-units).

P8

UI is an Editor Projection

The desktop IDE reads from the kernel and proposes actions through the kernel seam.

P9

Clean Concentric Architecture

Ring dependency structure enforced by Cargo workspace topology. No circular dependencies.

Repository Architecture

Cargo Workspace Crate Topology

EAK is structured into modular Rust crates with strict inward dependency edges toward eak-runtime.

CARGO WORKSPACE: 13 SPECIALIZED CRATESRust 1.74+ • Edition 2021
CORE KERNEL RING
  • eak-units: Typed physical quantities & tolerances
  • eak-domain: Entities, opaque EntityId, invariants
  • eak-ports: Abstract port traits & EventLog seam
  • eak-runtime: KERNEL: state/fold, FSM, replay engine
DOMAIN ENGINES RING
  • eak-engines: Planning, Schematic, PCB, DRC rules
  • eak-compiler: Requirement IR & Engineering IR lowering
  • eak-phases: FSM instances for each design phase
  • eak-assets: Footprints, 3D bodies, symbol libraries
ADAPTERS & PERIPHERALS RING
  • eak-reasoning: Multi-provider LLM adapters (NVIDIA/OpenAI)
  • eak-store: Append-only JSONL log & SQLite engine
  • eak-kicad: Bidirectional KiCad import/export adapter
  • eak-dashboard: Observability, telemetry & metrics
Verifiable Truth

Current Engineering Capability Matrix

In alignment with corporate governance standards, we clearly label current implementation statuses. We never present planned features as completed software.

Capability Domain / ModuleScope / Technical EvidenceStatus
Event-Sourced Engineering Runtime Core
Kernel & Runtime
Deterministic state machine (`RuntimeCore::commit`) with append-only event log, invariant validation, and deterministic replay.Implemented
Physical Quantities & Typed Unit System
Kernel & Runtime
Compile-time physical quantity validation (`eak-units`) with tolerances, unit conversion, and SI-derived dimensions.Implemented
Clean Architecture Port & Adapter Boundary
Kernel & Runtime
Ring dependency structure where kernel never depends on outer adapters, enforced at compile time via Cargo topology.Implemented
Desktop IDE Bridge (Tauri v2 Spine)
EDA Integration
Native desktop shell streaming live kernel events over `eak_ports::EventSink` to reactive desktop UI surfaces.Implemented
Multi-Provider Model Isolation Layer
Kernel & Runtime
Pluggable reasoning ports (`eak-reasoning`) supporting NVIDIA, OpenAI, and local offline inference models behind strict capability seams.Implemented
Component Asset Management & Schemas
Component Intelligence
Asset pipeline (`eak-assets`) managing symbol libraries, footprints, 3D bodies, and structured parametric attributes.Partially Implemented
KiCad Bidirectional Sync & Adapter
EDA Integration
Import/export adapter (`eak-kicad`) translating canonical engineering state to and from KiCad schematic/PCB files.Partially Implemented
Requirement & Engineering IR Compiler
Kernel & Runtime
Domain-specific lowering passes (`eak-compiler`) translating natural-language requirements into verified netlists and constraints.Partially Implemented
Rule-Based Verification Engine
Verification & Physics
Deterministic DRC, ERC, voltage-drop, and pin-constraint checkers (`eak-engines`) that validate AI proposals prior to commit.Partially Implemented
Automated Schematic Synthesis
Schematic Synthesis
Constraint-driven netlist synthesis and automatic multi-sheet schematic layout generation from engineering specs.Experimental
Autonomous PCB Component Placement
PCB Layout & Placement
Geometric thermal and signal integrity heuristics evaluating component floorplans and routing topology.Experimental
Automated DRC-Clean Autorouting
PCB Layout & Placement
Multi-layer high-density interconnect routing with deterministic return-path and differential-pair validation.Planned
Automated Fabrication Package Compiler
Manufacturing & BOM
One-click generation of verified Gerbers, drill tables, IPC-D-356 netlists, centroid files, and supply-chain audited BOMs.Planned
Development Trajectory

Master Implementation Roadmap

Dependency-driven stages with measurable exit gates per the canonical RFCs.

STAGE 00|Gate 0: Repository Clean & Verified Docs

Repository Reset & Canonical Foundations

Establish canonical documentation, clean architecture boundaries, branding, and comprehensive testing gates.

Clean workspace layout16 Canonical Architecture RFCsClean Cargo topology
Planned
STAGE 01|Gate 1: Developer Preview

Foundation Product & Tauri Spine

Native desktop IDE bridge connecting the Rust kernel event stream (`EventSink`) to real-time UI views.

Desktop IDE shell (Tauri v2)Live event streaming pipelineCanonical state viewer
Planned
STAGE 02|Gate 2: Real AI Engineering Workflow

Model Intelligence & Boundary Isolation

Standardized capability seams ensuring AI proposals never bypass deterministic engineering verification.

NVIDIA/OpenAI/Local providersValidated capability proposalsProvenance-tracked event logs
Planned
STAGE 03|Gate 3: Component-Aware Engineering

Component Intelligence & Parametric Search

Automated datasheet parsing, pin-matrix extraction, and verified library footprint mapping.

Datasheet parserParametric attribute graphStandardized footprints/symbols
Planned
STAGE 04|Gate 4: Schematic-Capable

Schematic Synthesis & Netlist Generation

Deterministic translation of high-level functional intent into formal schematic hierarchies and pin connections.

Hierarchical schematic engineERC validation suiteKiCad schematic sync
Planned
STAGE 05|Gate 5: PCB-Capable

PCB Physical Geometry & Placement

Physical constraint engine handling enclosure dimensions, keepouts, mechanical mounting, and copper geometry.

Board stackup editorThermal/signal placement engineKiCad PCB bidirectional sync
Planned
STAGE 06|Gate 6: Verified Engineering Workflow

Verification & Physics Engine

Multi-layer physics verification checking impedance, current density, signal timing, and manufacturing rules.

Impedance solverDRC rule evaluatorAutomated error remediation suggestions
Planned
STAGE 07|Gate 7: Autonomous Workflow Orchestration

Autonomous Multi-Agent Engineering Crew

Collaborative autonomous roles (Architecture, Component, Schematic, Routing, Verification agents) coordinated via runtime state.

Agent orchestration engineTask decomposition plannerHuman-in-the-loop audit gates
Planned
STAGE 08|Gate 8: Public V1

Manufacturing & Supply Chain Compilation

Exporting production-ready manufacturing packages with verified distributor stock availability and design-for-assembly checks.

Gerber / Drill generatorsBOM stock validationTurnkey assembly handoff packages
Planned
STAGE 09|Gate 9: Mature Engineering Platform

Product Maturity & Enterprise Workspace

Scalable multi-seat collaboration, versioned team libraries, enterprise on-premise execution, and private model support.

Team workspacesVersioned component repositoriesEnterprise security & audit controls
Planned

Auditable, Reproducible Electronics Engineering

The EAK prototype source code, documentation RFCs, and test suites are openly accessible on GitHub under NijoP/electronics-agent-kit-proto.